DV Engineer

Job Title: DV Engineer - 2-4 Yrs

Location: Bangalore

Experience required: 2-4 years

Education: B.E/B.tech/M.E/M.tech

Round of interviews: 2
R1: Virtual
R2: F2F(Both interviews will happen on the same day)


Primary Skills:

• Experience or exposure to Verilog, System Verilog, Object Oriented Programming/C++, Perl, and logic simulation is a requirement.
• Having UVM/OVM is mandatory.
• Must demonstrate strong Object-Oriented programming skills and concepts.

• Memory controller knowledge, Protocol knowledge

• Experience requires demonstrated technical expertise in functional verification, test planning, test bench development, stimulus generation, checking, and functional coverage.
• Experience or exposure to Verilog, System Verilog, Object Oriented Programming/C++, Perl, and logic simulation is a requirement
• Having UVM/OVM is an advantage .
• Must demonstrate strong Object Oriented programing skills and concepts. Any experience with memory controllers, dfi, dram memory models(ddr4/5, lpddr4/5, hbm, NVDIMM) and/or ddr phys is a plus.
• Requires strong communication skills and the ability to work independently as well as in a cross-site team environment.

KEY RESPONSIBILITIES:

• Develop, maintain and enhance test environment/regression, and testbench.
• Work on IP/block testing and debugging
• Work on functional code coverage, and performance/power testing.
• Support SoC integration and bridge the gap between IP and SoC