Staff Engineer Design System

Join us in shaping next-generation virtual platforms by developing high-performance SystemC/TLM2.0 models and QEMU-based virtual prototypes. Drive architecture, design, and simulation solutions that accelerate SoC and system validation.

Your role:

Key responsibilities in your new role:

• Responsible for virtual prototype and system modelling using SystemC/TLM2.0/CCI/UVM and industry standard ESL tools (e.g. Synopsys Virtualizer, ASTC, VLAB, etc.)
• Responsible for providing virtual prototype solutions for QEMU-based platforms
• Responsible for requirements analysis, SystemC model architecture, and high-level/low-level designs

Your profile:

Qualifications and skills to help you succeed:

• Background in C++/SystemC/TLM 2.0 on various development platforms (Windows/Linux, etc.)
• Development of functional/cycle approximate models using SystemC and tools such as Synopsys Virtualizer, ASTC, VLAB, etc. based on Visual Studio and g++ (for Linux)
• Verification of models using various methods, such as stand-alone SystemC-based unit verification, co-simulation with RTL (SystemVerilog), and software-based system testing
• Embedded system test development using C/C++ and automated execution/debugging
• Hands-on experience on embedded compilers such as GNU, Tasking, etc. and debuggers such as PLS, Lauterbach T32, etc.
• Background in machine learning and deep learning algorithms
• Ability to implement scalable and efficient AI systems