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    Job · 20756737

    HYDERABAD · FULLTIME

    RTL DESIGN and Verification Mentor for ETHERNET Protocol

    VL

    vlsicrest

    Hyderabad · onsite · Posted 11d ago

    Sourced fromFoundit
    Not disclosed6–8 yrsfulltimeHyderabad

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    Section · 01

    About this role

    WE'RE HIRING | ETHERNET PROTOCOL MENTOR

    VLSI CREST | INDUSTRY EXPERTS | REVENUE SHARING

    Do you have 6+ years of semiconductor industry experience and strong expertise in Ethernet protocol

    VLSI Crest is looking for an experienced Ethernet Protocol Mentor who can bridge the gap between theoretical knowledge and practical RTL Design and Design Verification skills.

    We're looking for an industry professional who understands Ethernet in depth and can mentor aspiring engineers through structured, hands-on learning.

    ROLE: ETHERNET PROTOCOL MENTOR

    EXPERIENCE

    • 6+ years of relevant industry experience.
    • Strong expertise in Ethernet protocol and its architecture.
    • Practical exposure to RTL Design, Design Verification or Ethernet IP development.
    • Ability to explain complex concepts through practical engineering examples.

    TECHNICAL EXPERTISE

    • Ethernet protocol architecture and fundamentals.
    • MAC architecture, packet transmission and reception.
    • Ethernet interfaces and protocol integration.
    • RTL microarchitecture and design considerations.
    • SystemVerilog-based verification and testbench development.
    • Protocol debugging, corner cases and verification strategies.

    WHAT WE EXPECT

    • Ability to develop a structured, industry-oriented curriculum.
    • Strong technical communication and mentoring skills.
    • Hands-on assignments, practical exercises and independently developed examples.
    • A commitment to helping students understand engineering decisions, debugging and design trade-offs.

    WHAT WE OFFER

    • Revenue-sharing collaboration.
    • Flexible, mutually agreed teaching schedules.
    • Opportunity to build and deliver specialized Ethernet training.
    • Collaboration with VLSI Crest to develop practical RTL Design and Verification programs.

    FOR CURRENTLY EMPLOYED ENGINEERS

    We respect your existing professional commitments. Mentoring must comply with your employment agreement, applicable company policies and any required outside-work approvals.

    All training must use original or properly licensed materials. Employer-confidential information, proprietary RTL, internal documents and restricted project details must not be disclosed or used.

    INTERESTED LET'S CONNECT.

    If you have 6+ years of experience and strong expertise in Ethernet protocol, I'd love to hear from you.

    Contact: [phone removed] (Call / WhatsApp) LinkedIn: DM me directly.

    Let's connect, collaborate and build industry-oriented Ethernet training for the next generation of RTL Design and Verification engineers.

    Please comment ETHERNET MENTOR or send a LinkedIn message with:

    1. Your years of relevant experience.
    2. Your Ethernet expertise and project background.
    3. Your RTL Design / Design Verification experience.
    4. Your availability for mentoring.
    5. Your preferred collaboration arrangement.

    Let's bring real engineering depth into the next generation of semiconductor talent.

    VLSI CREST

    Where Passion Meets Silicon Excellence — Empowering Future RTL Designers & Verification Engineers.

    • #Ethernet #VLSI #RTLDesign #DesignVerification #Semiconductor #TechnicalMentor #SystemVerilog #ASICDesign #Hiring

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    Section · 02

    Skills

    Ethernet interfaces and protocol integrationEthernet IP developmentEthernet protocol architecture and fundamentalsMAC architecturePacket transmission and receptionProtocol debugging corner cases and verification strategiesRTL microarchitecture and design considerationsSystemVerilog-based verification and testbench developmentRTL DesignDesign Verification

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