Power Engineer

Company: Qualcomm India Private Limited

Job Area: Engineering Group, Engineering Group > ASICS Engineering

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

• 2+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or a Master's degree.
• Understanding of RTL power optimization fundamentals, including switching activity, clock/enable efficiency, and common lowpower design patterns at the RTL level.
• Familiarity with RTL power analysis and optimization using tools such as PowerArtist, PTPX, PowerPro or equivalent.
• Familiarity with low-power design techniques, including clock gating, power gating, and managing dynamic vs. leakage power tradeoffs.
• Knowledge of Emulation Power flow and methodology.
• Knowledge of backend flows such as logic synthesis and placeandroute, and how RTL decisions impact postlayout power and timing.
• Hands-on experience of debugging RTL or gatelevel power anomalies and identifying rootcause structures or scenarios.
• Strong Python programming skills for building automation scripts, data pipelines, and AI/MLdriven analysis flows for RTL power optimization.
• Excellent debugging, analytical, and problem-solving skills using data-driven approach.
• Excellent written and verbal communication skills for documenting designs, methodologies, and best practices.
• Excellent collaboration skills, with the ability to navigate ambiguity in a fast-paced, global team environment.