PMIC Design Verification Lead (Sr Staff Engineer)

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

• Lead digital verification for next gen PMIC technologies, Mixed-Signals IPs, ASICs and Chipsets used in Qualcomm Snapdragon power solutions. IPs include telemetry ADCs, 100W+ charging (Quick Charge 5.0), 5G/6G power (mmW, envelope tracking, high-performance low noise oscillators etc) and high efficiency power management (DC-DC charge pumps, bucks and linear regulators).
• Work includes partnering with international teams in all stages of development from system definition to high-volume (100M+) OEM launches.
• Digital Verification aspects include all stages of the verification process, from test planning, UVM-compliant test-bench architecture, constrained random stimulus creation, score-boarding and coverage closure.
• Work includes verification of digital and mixed-signals IPs and exposure to analog behavioral models is a plus.
• Work includes debugging complex systems including SOCs, firmware, embedded sequencers.
• Position includes IP or chip digital DV ownership including task planning and project risk mitigation.
• Work in a dynamic team environment with an aggressive schedule towards metrics-based high-quality target.
• Experience in leading a team is a plus.

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
• Bachelor's degree in Science, Engineering, or related field. Masters preferred
• 10+ years ASIC design, verification, or related work experience

• Strong troubleshooting skills across ASIC systems disciplines (digital RTL, Firmware, analog behavioral models)
• Experience in writing Test Plans independently, planning Verification architecture, review testbench/ testplans with juniors, identify coverage gaps, propose alternate methods for coverage
• Strong communication and organizational skills
• Strong process-oriented mindset.
• Expert-level System Verilog Programming
• Advanced UVM/SV (Universal Verification Methodology using System Verilog)
• Python or Perl scripting