HYDERABAD · FULLTIME
DFT - Full Time
Kandou Ai
Hyderabad · onsite · Posted 12d ago
Sourced from
Not disclosed12–14 yrsfulltimeHyderabad
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Section · 01
About this role
Key Responsibilities:
- Lead DFT activity for the next generation products
- Driving the DFT architectures, methodologies and tool flows for complex multi-million gate designs with Analog/high bandwidth SerDes, DDR, PCIe designs
- Closely working with Physical implementation team to define timing constraints in test modes and helping to converge for successful tapeout
- Good understanding of ATE, knowledge of probe and final test bring up debug issues and drive the test engineering team for successful Silicon bring up and test program development
- Define the test plan by closely working with the design teams and drive the pattern development of functional/structural tests for final/wafer test program
- Closely working with the cross functional teams to bring up device qualification solution for HTOL
- Drive lab bench silicon debug to understand ATE bring up issues
- Excellent communication skills, and strong team player with can do type of attitude
- Mentoring the team members
- Excellent debugging skills
- Process oriented to drive automation to help increase productivity and quality
- 12+ years of DFT experience including architecture specification, implementation, test pattern development, and simulation
- Proven track record of delivering DFT solution to complex designs
- Experience working with IJTAG methodologies, understanding device functionality
- Experience with hierarchical MBIST insertion, hierarchical scan insertion and scan compression methodologies
- Experience in ATPG pattern generation for different kinds of fault models, fault coverage analysis and converging to high coverage metrics
- Strong debug capabilities in simulating patterns with timing
- Experience in defining test mode constraints and analyzing the timing reports
- Experience with industry standard EDA tools for DFT, timing, and simulation
- Good knowledge of System Verilog
- Experience with chiplet based designs is a plus
- Bachelor of Engineering in Electronics and Electrical Engineering, Computer Engineering or similar fields (equivalent or higher)
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Section · 02
Skills
Fault Coverage AnalysisEDA tools for DFT timing and simulationScan compression methodologiesAnalog high bandwidth SerDesfunctional structural testsIJTAG methodologiesDdrSystem VerilogPCIEscan insertionHTOLATEsilicon debugATPG Pattern generationDFT architecturesMBIST insertionTest Program Developmenttiming reports
Section · Company
About Kandou AI
Kandou Ai
Lausanne
CH
About
Kandou AI specializes in the design of high-speed, and pin- and energy-efficient chip-to-chip links, SerDes, and associated technologies. KANDOU specializes in the design of high-speed, and pin- and energy-efficient chip-to-chip links, SerDes, and associated technologies. Demand for bandwidth in serial links has increased as industries require both high-quantity and high-quality information. KANDOU BUS has developed a unique approach to serial link design that increases the bit-rate and the reach for a given physical communications link and reduces the power consumption. As a result, more bits can be sent per unit of energy, or less energy can be used to achieve a given bit rate. Less energy means available power can be used for more speed, greater battery life, smaller dies or novel designs that shatter many of today’s constraints. Their team of scientists and engineers, based in Switzerland, the UK, and the US, is pushing the boundaries of serial links.
Industries
Artificial Intelligence (AI)ElectronicsInformation TechnologySemiconductor
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