AMS Verification

AMS / Mixed-Signal Verification Engineer

Location: Bangalore, India

Experience: 2+ Years

Notice Period: Immediate to 60 Days

Role Overview

We are looking for a hands-on AMS / Mixed-Signal Verification Engineer to design, verify, and debug complex mixed-signal IPs (such as ADCs, DACs, LDOs, PLLs, SerDes, and GPIOs). You will work closely with design teams to build scalable testbenches, run co-simulations, and ensure functional coverage closure.

Key Responsibilities

• Behavioral Modeling: Develop block-level models using Verilog-AMS, SystemVerilog, or Real Number Modeling (RNM) for top-level mixed-signal simulations.
• Testbench Development: Build and maintain UVM-based testbenches, automated checkers, and constrained-random test environments.
• Co-Simulation: Run SPICE + Digital co-simulations for key AMS IPs.
• Debug & Coverage: Analyze waveform mismatches (WaveView, SimVision), debug interface/corner-case failures, and drive functional coverage to closure.

Key Requirements

• Experience: 2+ years of hands-on experience in AMS/Mixed-Signal design verification and debug.
• Languages & Methodologies: SystemVerilog, UVM, Verilog-AMS, SVA (SystemVerilog Assertions), and RNM (Real Number Modeling / WREAL).
• Tools Exposure:
• EDA Tools: Cadence Virtuoso, ADE Assembler, Xcelium/AMS, DiscoveryAMS, or Synopsys XA / PrimeSim.
• Debug/Regression: ViVA, SimVision, WaveView, vManager.