Verification Engineer
Luxoft · Hyderabad · onsite · Posted today
Undisclosed2–4 yrsfulltimeSourced from
About a minute. You'll make an account on the way through.
About this role
Project description
Responsibilities
Skills
Other
This is a great opportunity to work as part of a highly regarded team to deliver leading-edge solutions.
Responsibilities
- Tests the Xilinx Vivado FPGA implementation flow itself
- placer, routing, static timing analysis
- and analyses quality of results. EDA tool QA for an FPGA engineer, not ASIC verification.
Skills
Must have
- Xilinx Vivado, specifically the implementation flow
- FPGA design flow
- static timing analysis and design constraints
- digital / logic design
- debug skills
- 2-4 years of experience
- Experience: Minimum 2, maximum 4 years.
Nice to have
- EDA company experience
- scripting / automation (Tcl, Python)
- AI tool usage
Other
- Languages: English: B2 Upper Intermediate
- Seniority: Junior
Sourced from naukri
Skills
QAAutomationScriptingStatic Timing AnalysisFPGA DesignXilinxASIC VerificationLogic designASICVivadoEvent DrivenDebugPythonArtificial Intelligence
About Luxoft
Luxoft
IT Services & Consulting
2.3k+
employees
2000
26 years old
Zug, Switzerland
Switzerland
About
Luxoft offers the full spectrum of enterprise technology services, from modernizing legacy IT systems to delivering digital transformation at scale.
Industries
IT Services & Consulting
Employee ratings
832 reviews
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