Verification Engineer

Roles and Responsibilities :

• Design, develop, and execute test plans for complex digital circuits using SystemVerilog and UVM.
• Collaborate with cross-functional teams to identify requirements and create verification environments that meet customer needs.
• Develop reusable components such as scoreboards, monitors, and predictors to accelerate the verification process.
• Analyze results from simulations to identify defects in the design.

Job Requirements :

• 3-5 years of experience in system verification using SystemVerilog and UVM.
• Strong understanding of digital circuit design principles and protocols (e.g., PCIe).
• Experience with one or more industry-standard simulators (e.g., VCS) is required; knowledge of multiple simulators is a plus.