Verification Engineer - UVM/System Verilog
Tech Grow Global · Hyderabad · onsite · Posted 62d ago
Not disclosed6–10 yrsfulltimeSourced from
About a minute. You'll make an account on the way through.
About this role
Verification Engineer - UVM/System Verilog
Sourced from hirist
Skills
UVMSystem VerilogFPGAFunctional Verification