Verification Engineer- UVM/RTL/AMS

Our Team:

Semtech Corporation is a leading supplier of analog and mixed-signal semiconductors for high-end consumer, enterprise computing, communications, and industrial equipment. As our future market opportunities have increased in recent years, we have continued to invest in disruptive analog platforms and have created innovative new solutions for a wide range of leading edge products.

The Sensing Product Group located in our San Diego office has unique expertise in system level platform solutions for Sensing Products including Touch & Proximity. These are leading edge low power touch-interface solutions integrated with highly accurate ADCs for enhanced sensing performance. These ultra-small, feature-rich sensing systems are optimized for a wide range of battery-powered, portable applications such as smartphones, laptops, tablets, wearables, handheld devices and other consumer or ITA control applications.

Job Summary:

The Verification Engineer is responsible for developing tests and running verification regressions that will ensure the functionality and performance of Semtechs next generation sensing products. Within the verification team and working closely with the rest of the design team, she/he develops, runs and debugs RTL, gate-level and analog mixed signal tests through the full design cycle.

Responsibilities:

• Perform block and chip-level verification in register-transfer level (RTL), gate-level and analog/mixed-signal (AMS).
• Run digital/mixed-signal simulations as well as formal verification.
• Work closely with the design team to create verification strategy and detailed verification plan.
• Develop tests, run regressions and monitor coverage to ensure tape-out quality.
• Participate in design or project reviews and support these with verification perspective and schedule/priority assessment.
• Support post-silicon bring-up and debug, for bench validation as well as automated test equipment (ATE) testing.
• Improve verification scalability and portability from project to project by environment enhancement and tools automation.

Minimum Qualifications:

3+ years experience in semiconductor industry

• M.S. in EE/CS/CE or higher
• Hands-on experience with System Verilog as High-level Verification Language and UVM implementation.
• Debugging digital simulation in both RTL and gate-level netlist, isolating issues in both module and system level.
• Scripting experience in Python or Perl.
• Clear understanding of ASIC design flow
• Solid analytical and problem solving skills
• Independent, self-motivated, rigorous, team player and able to follow through
• Excellent verbal and written communication skills

Desired Qualifications

Experience of setting up UVM verification environment from scratch

• Familiarity with VHDL or System Verilog RNM
• Automation of verification flow with Python/Perl in industrial setting
• Analog behavioral model development/verification experience