HYDERABAD · FULLTIME
Verification Engineer - ASIC Design
IIT Hyderabad
Hyderabad · onsite · Posted 75d ago
Sourced from
Not disclosed2–11 yrsfulltimeHyderabad
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Section · 01
About this role
Verification Engineer - ASIC Design
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Section · 02
Skills
UVMSystem VerilogASICDesign Verificationverification
Section · Company
About IIT Hyderabad
IIT Hyderabad
₹5.2L PA avg
Avg at IIT Hyderabad
Employee ratings
10 reviews
4.3/ 5
Culture
4.3
Career growth
3.0
Work-life
4.2
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Skill Development43Overall Company43
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