Turing-IP Design Verification - Sr Engineer

Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group > Hardware Engineering

General Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
  
  

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

About The Role

We are looking for a skilled and motivated DV Engineer to join our IP verification team. In this role, you will be responsible for the functional verification of complex IPs and subsystems that form the building blocks of our next-generation SoCs. You will work closely with design, architecture, and SoC integration teams to define verification strategies, build robust testbenches, and drive coverage closure to deliver high-quality silicon.

Key Responsibilities

• Own and drive functional verification of IPs and subsystems from planning through sign-off.
• Develop verification plans, testbench architecture, and test cases based on design and architecture specifications.
• Build and enhance reusable, scalable verification environments using System Verilog and UVM.
• Develop and maintain constrained-random and directed test scenarios, assertions, and functional coverage models.
• Drive coverage closure (code + functional) and debug failures using waveform/log analysis.
• Collaborate with design, architecture, and SoC integration teams to resolve issues and ensure verification completeness.
• Contribute to regression setup, triage, and maintenance to ensure verification quality and throughput.
• Support IP-to-subsystem-to-SoC integration and reuse of verification collateral across levels.
  
  

Required Qualifications

• 3 to 5 years of hands-on experience in ASIC/SoC functional verification.
• Strong proficiency in System Verilog and UVM methodology.
• Proven experience in IP, subsystem, and/or SoC-level verification.
• Solid understanding of verification concepts: constrained-random stimulus, functional coverage, assertions (SVA), and scoreboarding.
• Strong debug skills using simulation logs and waveform tools (e.g., Verdi/FSDB).
• Good understanding of digital design fundamentals, bus protocols, and SoC architecture.
• Strong analytical, problem-solving, and communication skills.
  
  

Preferred / Good-to-Have Skills

Experience in integration of C/C++ models into SV UVM Testbench using SVC DPI calls

Familiarity with formal verification(C2RTL, FPV..) and performance verification.

Experience with industry-standard bus protocols (AXI/AHB/APB, etc.).

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