Turing-Design Verification Sr Lead Engineer

About the Role Bachelor''s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster''s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.Key Responsibilities

• Own and drive functional verification of IPs and subsystems from planning through sign-off.
• Develop verification plans, testbench architecture, and test cases based on design and architecture specifications.
• Build and enhance reusable, scalable verification environments using System Verilog and UVM.
• Develop and maintain constrained-random and directed test scenarios, assertions, and functional coverage models.
• Drive coverage closure (code + functional) and debug failures using waveform/log analysis.
• Collaborate with design, architecture, and SoC integration teams to resolve issues and ensure verification completeness.
• Contribute to regression setup, triage, and maintenance to ensure verification quality and throughput.
• Support IP-to-subsystem-to-SoC integration and reuse of verification collateral across levels.

Required Qualifications

• 4-6 years of hands-on experience in ASIC/SoC functional verification.
• Strong proficiency in System Verilog and UVM methodology.
• Proven experience in IP, subsystem, and/or SoC-level verification.
• Solid understanding of verification concepts: constrained-random stimulus, functional coverage, assertions (SVA), and scoreboarding.
• Strong debug skills using simulation logs and waveform tools (e.g., Verdi/FSDB).
• Good understanding of digital design fundamentals, bus protocols, and SoC architecture.
• Proficiency in scripting (Python/Perl/Tcl) for automation and flow development.
• Strong analytical, problem-solving, and communication skills.

Preferred / Good-to-Have Skills

• Experience with low-power verification (UPF/Power-aware) flows.
• Exposure to Gate-Level Simulation (GLS) including timing and SDF-based verification.
• Familiarity with formal verification, emulation, or performance verification.
• Experience with industry-standard bus protocols (AXI/AHB/APB, etc.).