Technical Staff Engineer - CAD

Responsibilities

• Function: You will work on industry standard CAD activities for the state of art next generation Microchip FPGA devices. These devices contain RiscV CPUs and all the associated functions to create true SOC functionality. It is expected that the successful candidate will be able to Work closely with Microchip teams such as Engineering Services, Design teams, and Operations, to ensure Microchip s design flows and tools are robust and reliable. Provide front line support for Microchip staff in the use of these tools and flows. Provide an interface with external tool vendors and suppliers to resolve issues and provide guidance as needed.

Skills

• In-depth experience with setting up Cadence full-custom design environment (in both Virtuoso 12, Virtuoso Studio IC 23.1 and above).
• Understanding of 12nm/ lower process technologies, including FinFet.
• Experience in handling standard cell libraries and pdk installations.
• Experience with Pcell creation, debugging, and migration flows.
• Experienced in SKILL/Perl/Python scripting for design automation.
• Experience in writing DRC/LVS runsets for Physical verification flows using Mentor Calibre
• Experience in debugging AMS/Custom Design EDA tool issues
• Work with CDL, hspiceD and Verilog netlisting customizations.
• In-depth knowledge of Cadence VXL and assist layout engineers resolve VXL issues.
• Setup and debug LSF/DesignSync issues.
• Develop, test, and release scripts and tools as specified to aid in analog design
• Support with/Involving in Tape-out activities and foundry interface.
• Experience in using AI tools to speed up the deliverables

Requirements/Qualifications

• BSEE or MSEE and 12+ years of relevant work experience.
• Interface with cross-functional teams on various CAD requests.
• Good communication skills for coordinating tasks across all different sites in different time zones.

Travel Time


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