Technical Manager - Analog Layout
Questa Global · Bengaluru · onsite · Posted 29d ago
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About this role
Job Requirements
Position: Analog Layout Technical Manager
Job Responsibilities
Lead and mentor a team of Analog Layout Engineers.
Own analog and mixed-signal layout activities from planning to tape-out.
Review layouts for matching, parasitic optimization, ESD, latch-up, EM/IR, and reliability requirements.
Drive floorplanning, layout architecture, and methodology improvements.
Ensure clean DRC, LVS, ERC, and other physical verification sign-offs.
Work closely with Analog Design, Verification, CAD, and Product teams.
Support project planning, effort estimation, schedule tracking, and risk management.
Conduct technical reviews and support customer discussions when required.
Guide engineers on best practices for quality, performance, and area optimization.
Required Skills
Strong experience in Analog/Mixed-Signal Layout.
Hands-on expertise with Cadence Virtuoso and physical verification tools such as Calibre.
Good understanding of matching, shielding, parasitic effects, ESD, latch-up, and reliability.
Experience in advanced CMOS/FinFET technology nodes.
Strong leadership, communication, and stakeholder management skills.
Preferred
Experience in PMIC, ADC, DAC, PLL, Bandgap, LDO, SerDes, or RF layouts.
Experience managing a team and delivering full-chip or subsystem tape-outs.
Exposure to customer-facing projects and global teams
Work Experience
Strong experience in Analog/Mixed-Signal Layout.
Hands-on expertise with Cadence Virtuoso and physical verification tools such as Calibre.
Good understanding of matching, shielding, parasitic effects, ESD, latch-up, and reliability.
Experience in advanced CMOS/FinFET technology nodes.
Strong leadership, communication, and stakeholder management skil
Position: Analog Layout Technical Manager
Job Responsibilities
Lead and mentor a team of Analog Layout Engineers.
Own analog and mixed-signal layout activities from planning to tape-out.
Review layouts for matching, parasitic optimization, ESD, latch-up, EM/IR, and reliability requirements.
Drive floorplanning, layout architecture, and methodology improvements.
Ensure clean DRC, LVS, ERC, and other physical verification sign-offs.
Work closely with Analog Design, Verification, CAD, and Product teams.
Support project planning, effort estimation, schedule tracking, and risk management.
Conduct technical reviews and support customer discussions when required.
Guide engineers on best practices for quality, performance, and area optimization.
Required Skills
Strong experience in Analog/Mixed-Signal Layout.
Hands-on expertise with Cadence Virtuoso and physical verification tools such as Calibre.
Good understanding of matching, shielding, parasitic effects, ESD, latch-up, and reliability.
Experience in advanced CMOS/FinFET technology nodes.
Strong leadership, communication, and stakeholder management skills.
Preferred
Experience in PMIC, ADC, DAC, PLL, Bandgap, LDO, SerDes, or RF layouts.
Experience managing a team and delivering full-chip or subsystem tape-outs.
Exposure to customer-facing projects and global teams
Work Experience
Strong experience in Analog/Mixed-Signal Layout.
Hands-on expertise with Cadence Virtuoso and physical verification tools such as Calibre.
Good understanding of matching, shielding, parasitic effects, ESD, latch-up, and reliability.
Experience in advanced CMOS/FinFET technology nodes.
Strong leadership, communication, and stakeholder management skil
Sourced from foundit
Skills
ESD latch-upadvanced CMOS FinFET technology nodescadence virtuosoCalibrereliabilityshieldingmatchingparasitic effectsAnalog/Mixed-Signal Layout
About Questa Global
Questa Global
Recruitment
11-50
employees
2010
16 years old
Gurgaon
India
₹10.6L PA avg
Avg at Questa Global
About
Questa Global provides comprehensive business management solutions, leveraging extensive industry experience to enhance human capital services and organizational performance.
Industries
Recruitment
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4.0/ 5
Culture
3.9
Career growth
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Work-life
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