Technical Lead I - VLSI ML ST

Responsibilities

• SRAM bitcell layout
• memory peripherals layout (Row/Column Decoders, Sense Amplifiers, Pre-charge, Write Drivers, Read/Write Assist, IO and Self-Timing)
• Single-Port SRAM, Dual-Port SRAM and ROM architectures
• full memory macro floorplanning and block integration
• critical signal routing
• parasitic-aware layout techniques
• DRC, LVS, ERC and parasitic extraction
• power grid design, decoupling capacitance and power sequencing
• post-layout extracted simulations and optimization
• Experience with industry-standard custom layout and physical verification tools
• Exposure to advanced technology nodes and SRAM compiler development is preferred
• Experience

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.