Tcs Hiring For Senior Static Timing Analysis Engineer/Lead

Role: Senior Static Timing Analysis Engineer/Lead

Required Technical Skill :

Strong understanding of advanced STA concepts and challenges in advanced technology nodes such as 5nm, 3nm and 2nm. Thorough knowledge of the ASIC design cycle and timing closure flow and methodology. Proficiency in timing constraints and timing closure. Expertise in STA tools (any of Primetime, Tempus, Tweaker) and flow. Proficiency scripting languages (TCL, Perl, Python). Strong background in Implementation and Extraction domain.

Must-Have**

Proficiency in RTL to GDS flows and methodologies, with significant experience in advanced nodes (7nm, 5nm, 3nm or below). Working knowledge of scripting languages (Perl, TCL, AWK, Python). Strong interpersonal skills and the ability to work effectively in a collaborative team environment. Good verbal and written communication skills.

Good to Have

Experience of constraints development tool (like spyglass) will be added advantage. Excellent understanding of logic design fundamentals and gate/transistor level implementation. Exposure to DFT is an asset. Prior experience working on high performance technology nodes and understanding of deep sub-micron design problems/solutions. Strong problem solving and debug skills across various levels of design hierarchies.