SystemC/TLM SoC Modelling Engineer

Job Description: SystemC/TLM SoC Modelling Engineer (2-5 Years Experience)
We are looking for a SystemC/TLM SoC Modelling Engineer with 2-5 years of hands-on experience to develop high-level virtual platforms and transaction-level models for complex System-on-Chip (SoC) architectures.
Key Responsibilities:
• Develop, integrate, and validate SystemC/TLM 2.0 models for SoC components (CPUs, interconnects, peripherals, memory subsystems).
• Create functional, performance, and loosely-timed (LT) / approximately-timed (AT) models for architecture exploration, hardware-software co-verification, and early software development.
• Collaborate with architecture, design, and verification teams to ensure model accuracy and performance.
• Debug and optimize simulation speed vs. timing fidelity trade-offs.
Required Skills & Qualifications:
• Strong proficiency in C++ (C++11 and modern standards) and SystemC/TLM-2.0 for modelling.
• Solid understanding of SoC architecture (processors, caches, coherency protocols, interconnects, memory ordering).
• Experience with virtual platforms, performance modelling, and hardware-software co-simulation.
• Good knowledge of digital design concepts, protocols (e.g., AXI, ACE), and verification methodologies.
• Bachelors/Masters degree in Electronics, Computer Engineering, or related field.
Nice-to-Haves:
• Exposure to tools like Synopsys Virtualizer, Cadence, or open-source SystemC environments.
• Familiarity with Python scripting, Git, and agile development.