Synthesis Engineer
Einfochips · Bengaluru · onsite · Posted 58d ago
Undisclosed5–10 yrsfulltimeSourced from
About a minute. You'll make an account on the way through.
About this role
5 to 10 years of experience in RTL Synthesis, Timing Constraints / SDC checking / reviewing / small fixes / finding errors etc. Should have done at least 3 ASIC projects.
CDC, Lint clean up and automation with scripts.
Timing Report analysis, Static Timing Analysis
Tools :
Genus / FC : Synthesis, Optimization or DC compiler, DCTopo
Spyglass : Constraints checking / CDC Checking
LEC / Formality : Formal Verification, VCLP.
Primetime : Zero delay Timing analysis
Sourced from naukri
Skills
Static Timing AnalysisPrimetimeSTAsynthesisDesign CompilerGenusRTL synthesisASIC Synthesis
About Einfochips
Einfochips
IT Services & Consulting
3.2k+
employees
1994
32 years old
San Jose, California
United States (USA)
About
eInfochips, an Arrow company, is a product engineering and semiconductor design services firm, specializing in digital transformation and connected IoT solutions across various cloud platforms.
Industries
IT Services & ConsultingDesignEngineering & Construction
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