Structural DFT Engineer

THE ROLE

The Test Development team is driving quality and manufacturability for some of the industry s most advanced MPSoC designs at 7nm and beyond. As a Member Technical Staff(MTS) Silicon Design Engineer, you will play a pivotal role in shaping how complex, high-performance silicon is tested, validated and delivered to customers across automotive, data center, machine learning and high-speed connectivity markets.

This role offers deep, hands-on exposure to Scan, MBIST and iJTAG test development on large, heterogeneous SoCs that integrate ARM-based processors alongside critical, high-value IPs. You will work at the intersection of design, test and manufacturing - partnering closely with RTL designers to ensure robust DFT insertion, collaborating with test engineers to translate DFT intent into scalable ATE programs and engaging with product and yield teams to enable stable, high-volume production. The environment is fast-paced, highly collaborative and impact-driven, offering strong technical ownership, continuous learning and visibility across the full silicon lifecycle.

THE PERSON

You are a strong communicator and team player who thrives in a globally distributed, collaborative environment. You embrace technical challenges, adapt quickly to changing priorities and take ownership of complex problems through to resolution. A proactive mindset, curiosity to learn and commitment to quality are key to success in this role.

KEY RESPONSIBILITIES

• Partner closely with RTL design teams to define, review and ensure correct insertion of DFT architectures across SoC and IP designs.
• Develop, implement and verify robust DFT schemes for hard IPs and FPGA-based designs.
• Own test development for digital logic using scan compression and multiple fault models, including stuck-at, transition and path-delay.
• Develop and validate MBIST architectures and patterns to ensure high coverage and production readiness.
• Lead debugging of scan, MBIST and pattern-related issues on bench and ATE, driving root-cause analysis and resolution.
• Collaborate with NPI, Test Engineering and Product teams to deliver high-quality, production-ready test content on schedule.
• Support diagnosis and yield improvement efforts throughout the product lifecycle.
• Design and implement firmware-driven, cost-effective test strategies with built-in diagnostic capabilities.
• Optimize test methodologies to improve coverage, reduce test cost and enhance overall product quality.
• Contribute to continuous improvement by mentoring team members and sharing best practices.

PREFERRED EXPERIENCE

• Experience designing and implementing complex, chip-level DFT architectures for advanced SoCs.
• Hands-on experience with DFT implementation, including Scan and Scan Compression, at IP and SoC levels.
• Experience using DFT and ATPG tools across stuck-at, at-speed and path-delay fault models.
• Proficiency in RTL logic design using Verilog, with working knowledge of synthesis and static timing analysis.
• Experience developing testbenches and running simulations in RTL, gate-level and SDF environments.
• Working knowledge of MBIST architectures and pattern development is preferred.
• Familiarity with FPGA design and synthesis flows is a plus.
• Exposure to post-silicon debug, bench setup and ATE-based validation is a plus.
• Comfortable working in Linux environments and using scripting languages such as Perl, Tcl or Python.

ACADEMIC CREDENTIALS

• Bachelor s or Master s degree in Electrical Engineering, Electronics Engineering, Computer Engineering or a related field is preferred.
• Formal education or training with a focus on digital design, DFT or test methodologies is desired.