Std Cell Layout Engineer

Location: Noida, Uttar Pradesh

Experience: 4+ Years

Employment Type: Full-time

Job Overview

The role involves development, optimization, and physical verification of standard cell libraries for advanced semiconductor technologies. The engineer will work closely with circuit designers, characterization, library, physical design, and technology teams to deliver high-quality, PPA-optimized standard cells meeting stringent performance, power, area, and manufacturability requirements.

Key Responsibilities

• Design and develop physical layouts for standard cells including combinational and sequential logic cells.
• Work on different standard cell variants such as NAND, NOR, INV, BUF, AOI/OAI, MUX, XOR/XNOR, Flip-Flops, Latches, Tie cells, Level Shifters and related library cells.
• Perform full-custom layout of standard cells based on schematics and technology requirements.
• Optimize cell layouts for area, timing, power, routability and overall PPA.
• Ensure proper cell architecture, device placement, diffusion sharing, pin accessibility and routing while maintaining design-rule compliance.
• Perform DRC, LVS, ERC and other physical verification activities and resolve violations.
• Work with circuit designers to understand electrical requirements and translate schematics into robust, manufacturable layouts.
• Analyze and resolve layout-related issues affecting timing, power, leakage, parasitics and signal integrity.
• Support development and optimization of standard-cell libraries across different process technologies and PVT conditions.
• Collaborate with characterization teams for timing, power and functionality validation of standard cells.
• Support cell benchmarking and PPA analysis against existing/reference libraries.
• Participate in library development activities from layout implementation through physical verification and release.
• Work closely with global teams across design, technology, characterization and physical design.
• Develop or use scripting/automation wherever applicable to improve layout and verification productivity.

Required Skills & Experience

• 4+ years of relevant experience in Standard Cell Layout / Library Development.
• Strong hands-on experience in standard cell physical layout.
• Good understanding of CMOS circuits, transistor-level design and semiconductor device fundamentals.
• Strong knowledge of standard-cell architecture and layout techniques.
• Hands-on experience with:
• Cadence Virtuoso / Layout XL
• Calibre DRC/LVS or equivalent physical verification tools
• Strong understanding of:
• DRC / LVS / ERC
• Design-rule constraints
• PPA optimization
• Device matching and layout-dependent effects
• Parasitics and their impact on circuit performance
• Pin accessibility and routing considerations
• Experience working with advanced technology nodes is preferred.
• Good understanding of different combinational and sequential standard cells.
• Ability to debug physical verification issues independently.
• Good communication and cross-functional collaboration skills.

Good to Have

• Experience in standard-cell library development / characterization.
• Exposure to Liberty (.lib) generation and characterization flows.
• Knowledge of timing and power characterization using tools such as Liberate / SiliconSmart.
• Exposure to PrimeTime / STA or other timing-analysis tools.
• Understanding of PVT corners, setup/hold, slew, load and timing arcs.
• Experience with FinFET / advanced-node technologies.
• Knowledge of DTCO / library optimization concepts.
• Scripting experience in Python, Perl, TCL or SKILL.
• Exposure to digital implementation / RTL-to-GDS flow.
• Experience working with high-performance or low-power standard-cell libraries.

Educational Qualification

• B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, VLSI or a related discipline.