Staff VLSI Design Engineer (CAD)

• Responsible for the further development of concepts and methods for the EDA design environments with focus on analog / mixed signal CAD flows.
• Expert level proficiency in one or more of the programming/scripting languages - SKILL, Python, Unix, Perl and TCL.
• Expertise in Virtuoso suite of tools and Analog Design environment (finesim/PrimeSim)
• Solid understanding of Calibre Physical Verification rule deck (SVRF) and ICV LVS decks with hands on experience in integrating various PV flows in CAD environment.
• Solid experience in Layout Automation and Utilities development in Cadence SKILL/SKILL++.
• Development and validation of PV tools and flows like parasitic extraction, EMIR drop and substrate noise analysis.
• Responsibilities will include testing, validation, customer support and new tool/methods evaluations, development of methods and procedures for quality improvement, automation of deck/tech Files generation and validation.
• Experience with Cadence custom IC Virtuoso platform to create layout test structures, to validate verification rules and to troubleshoot errors.
• Experience with physical verification tools for parasitic extraction (starRC) is a plus.
• Working knowledge of revision control software (Git, Perforce, Synchronicity, etc)
• Ensuring the operation and support within the CAD for layout and circuit designers worldwide.
• Develop and deploy agentic AI flows to automate flow execution, detect bottlenecks, triage violations, and drive closure decisions without manual intervention

Qualifications