Staff Verification Engineer

Roles and Responsibilities :

• Design and develop verification plans, testbenches, and scripts for complex digital circuits using SystemVerilog.
• Collaborate with cross-functional teams to identify requirements and create functional models of the design under test (DUT).
• Conduct thorough debugging of issues found during testing, working closely with the development team to resolve problems.
• Develop expertise in specific areas such as STA (Static Timing Analysis) or other relevant technologies.

Job Requirements :

• 6-10 years of experience in Verification Engineering with a focus on semiconductor industry.
• Strong understanding of SystemVerilog programming language and its applications in verification.
• Experience with static timing analysis (STA) tools such as VCS or similar products.