Staff Physical Design Engineer

Staff Physical Design Engineer

Location: Bengaluru

Experience: 8–12 Years

Employment: Full-time

Role Overview

We are looking for a Staff Physical Design Engineer with strong expertise in full-chip physical implementation, timing closure, and Innovus. The ideal candidate will own critical aspects of physical design from netlist to GDSII, drive PPA optimization, and lead complex timing/debug challenges across advanced SoC designs.

Key Responsibilities

• Own full-chip physical design from floorplanning through placement, CTS, routing, optimization, and signoff.
• Drive PPA optimization across performance, power, and area.
• Strong hands-on implementation experience using Cadence Innovus.
• Perform STA, timing analysis, and timing closure across multiple PVT/MMMC scenarios.
• Analyze and resolve setup/hold violations, congestion, IR/EM-related issues, and signal integrity challenges.
• Work closely with RTL, synthesis, STA, DFT, and physical verification teams to resolve design issues.
• Drive clock-tree synthesis, clock optimization, useful skew, and high-quality clock distribution.
• Handle full-chip integration, block-level interfaces, hierarchical implementation, and top-level timing closure.
• Develop/debug Tcl/Perl/Python automation for implementation, analysis, and flow improvement.
• Contribute to methodology improvements and mentor junior engineers.

Required Qualifications

• 8–12 years of hands-on experience in Physical Design.
• Strong full-chip / top-level SoC physical design experience.
• Excellent hands-on expertise with Cadence Innovus.
• Strong understanding of STA and timing closure methodologies.
• Solid experience with floorplanning, placement, CTS, routing, optimization, and signoff.
• Strong knowledge of MMMC, SDC constraints, timing ECOs, and PVT analysis.
• Experience debugging complex setup/hold, congestion, clock, and routing issues.
• Strong understanding of physical design fundamentals and advanced-node challenges.
• Proficiency in Tcl scripting; Python/Perl knowledge is a plus.
• Strong problem-solving, ownership, and cross-functional collaboration skills.

Good to Have

• Experience with high-performance / low-power SoCs.
• Exposure to PrimeTime, Tempus, Voltus, Quantus, or equivalent signoff tools.
• Experience with IR/EM, crosstalk/SI, physical verification, and ECO implementation.
• Experience driving PD methodologies and flow automation.
• Experience leading complex blocks or full-chip PD execution.