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    Job · 13649650

    SanDisk India Device Design Centre logo

    Staff Engineer, VLSI Design Engineering (UVM, System Verilog) with 8 to 12 years of experience

    SanDisk India Device Design Centre · Bengaluru · onsite · Posted 59d ago

    Not disclosed8–12 yrsfulltimeSourced fromFoundit

    About a minute. You'll make an account on the way through.

    About this role

    Company Description

    Sandiskunderstands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today's needs and tomorrow's next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we're living in and that we have the power to shape.

    Sandiskmeets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibilityforward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globallyforinnovation, performance and quality.

    Sandiskhas two facilities recognized by the World EconomicForum as part of the Global Lighthouse Networkforadvanced 4IR innovations. These facilities were also recognized as Sustainability Lighthousesforbreakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world movingforward.

    Job Description

    Job responsibilities:

    • Lead the development and execution of comprehensive test plans, verification strategies, and verification infrastructure for complex IP blocks, sub-systems, and SoC designs
    • Design and implement verification environments using industry-standard UVM (Universal Verification Methodology) frameworks
    • Develop reusable and scalable verification components, including bus functional models, monitors, checkers, and scoreboards
    • Drive functional coverage-driven verification closure and ensure comprehensive design validation including Functional Coverage planning, development, debug and closure
    • Develop and maintain System Verilog Assertions (SVA) for design verification, including coding, porting, and maintenance activities
    • Collaborate with design architects, RTL designers, and post-silicon validation teams to ensure seamless verification integration
    • Create and optimize verification automation tools and scripts to enhance design and verification productivity
    • Investigate, debug, and perform root-cause analysis of design failures through cross-functional team collaboration
    • Mentor junior engineers and contribute to the continuous improvement of verification methodologies and best practices

    Qualifications

    8 to 12 years of relevant experience

    • Education:

    B.E/B.Tech/M.Tech in ECE/VLSI/Electrical Engineering

    Skills Required/Preferred

    • Bachelor's degree in Electronics and Communication Engineering (ECE), VLSI, or Electrical Engineering; Master's degree preferred
    • Advanced proficiency in C, Verilog, SystemVerilog, and UVM (Universal Verification Methodology)
    • Hands-on experience with industry-standard verification tools including Xcellium, Verdi, and JasperGold formal verification tools
    • Demonstrated expertise across the complete verification lifecycle, including planning, testbench development, test case development, regression management, coverage analysis, debugging, and sign-off
    • Proven ability to lead technical projects and manage stakeholder relationships effectively
    • Bring in AI/ML/Automation based initiatives
    • Excellent written and verbal communication skills with demonstrated ability to adapt to dynamic project requirements and deliver results under challenging schedules
    • Preferred Qualifications:
    • Experience with NAND flash memory protocols and memory design verification
    • Track record of mentoring junior engineers and contributing to process improvements
    • Experience with formal verification methodologies and assertion-based verification

    Tools Experience/exposure

    • Xcelium simulator, Verdi Debugger, Jaspergold Formal, Vmanager Regression manager
    • Relevant end to end Verification tools exposure from leading EDA vendors

    Additional Information

    Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.

    Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us [HIDDEN TEXT] advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

    Sourced from foundit

    Skills

    cVerilogUVMSystem VerilogXceliumVerdiJaspergold

    About SanDisk India Device Design Centre

    SanDisk India Device Design Centre logo

    SanDisk India Device Design Centre

    Hardware & Networking

    2.3k+

    employees

    2005

    21 years old

    San Jose

    United States Of America

    ₹21.1L PA avg

    Avg at SanDisk India Device Design Centre

    About

    A subsidiary of Western Digital, specializing in innovative data solutions that facilitate data accessibility and transformation across various industries.

    Industries

    Hardware & Networking

    Employee ratings

    10 reviews

    3.8/ 5

    Culture

    3.5

    Career growth

    3.0

    Work-life

    3.8

    Employees rate it well for

    Company Culture39Work-Life Balance39

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    Staff Engineer, VLSI Design Engineering (UVM, System Verilog) with 8 to 12 years of experience · waiting for your command