{"@context":"https://schema.org","@type":"JobPosting","title":"STA & Synthesis Engineer","description":"

Job Summary:

We are looking for an STA & Synthesis Engineer responsible for timing analysis and logic synthesis of digital designs.
The role focuses on achieving timing closure and optimizing design performance, power, and area.

Key Responsibilities:

\tPerform RTL synthesis using industry-standard tools
\tShould be capable to analyze and run LEC to ensure gate level netlist matches the original RTL
\tRun Static Timing Analysis (STA) and identify timing violations
\tFix setup and hold violations across different corners/modes
\tWork on constraints development (SDC creation and validation)
\tAnalyze timing reports and improve design quality
\tCollaborate with RTL, DFT, and Physical Design teams
\tSupport timing closure during implementation and signoff

Required Skills:

Strong understanding of digital design fundamentals
\tKnowledge of synthesis and STA flow
\tFamiliarity with timing concepts (setup, hold, skew, latency)
\tExperience with EDA tools (Experience with EDA tools
(Genus, Tempus).

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