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    Job · 13716597

    HYDERABAD · FULLTIME

    Sta Engineer

    Allegis Group logo

    Allegis Group

    Hyderabad · onsite · Posted 57d ago

    Sourced fromNaukri
    Undisclosed5–7 yrsfulltimeHyderabad

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    Section · 01

    About this role

    We are Hiring STA Engineer

    Location: Hyderabad, India
    Experience: 5+ Years

    Hiring for Product based company

    Job Description:

    Top 3 skills:
    •STA Engineers, Constraint writing of different timing modes,
    Static timing analysis of different modes,
    Formality & LEC

    Key Skills Required
    • Strong experience in Constraint Development.
    • Hands-on experience with Static Timing Analysis (STA).
    • Experience in:
    Pre-layout and Post-layout STA checks
    Check Timing
    No Clock checks
    Constraint endpoint checks
    Constraint validation and analysis
    • Prime Time is the preferred STA tool.
    • Exposure to LEC/Formality is a plus but not mandatory.

    • Good to have (secondary) skills: Timing CDC crossing understanding
      • Conformal or Netlist based ECO implementation
      Soft Skills • Strong communication skills and able to interact with different cross functional teams
      Education Background B.Tech / M.Tech in Electronics, VLSI or related field

    We are looking for an experienced STA Engineers to join our team in Hyderabad. In this role, you will learn and contribute to implementation activities like timing constraints, STA, logical equivalence check etc. You will get hands-on exposure to industry standard tools and methodologies while working alongside experienced engineers.

    Job Responsibilities / Day-to-Day Activities
    • Should be able to develop constraints for different timing modes like Functional, Scan shift etc
    • Able to do static timing checks like check timing, update timing and able debug issues in this
    • Should be able to debug Formality/Conformal logical equivalence check (LEC)

    Qualifications & Experiences:
    • B.E/B.Tech/M.Tech in Electronics, VLSI or related field.
    • Strong understanding of digital logic design and timing constraints & STA.
    • Understanding of Verilog
    • Familiartiy with EDA tools and scripting

    Interested candidates please send your CV along with your current CTC, expected CTC, and notice period to [email removed]

    Sourced from naukri

    Section · 02

    Skills

    PrimetimeSTASDCTiming Constraintsconstraint development

    Section · Company

    About Allegis Group

    Allegis Group logo

    Allegis Group

    Recruitment

    913

    employees

    1983

    43 years old

    Hanover, Maryland

    United States (USA)

    About

    Allegis Group provides comprehensive talent solutions, enhancing workforce strategies and connecting individuals with career opportunities on a global scale.

    Industries

    Recruitment

    Employee ratings

    448 reviews

    3.5/ 5

    Culture

    3.5

    Career growth

    2.8

    Work-life

    3.6

    Employees rate it well for

    Salary64Work Culture48Work Life Balance33Job Security32Work Environment32

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    Sta Engineer · waiting for your command