STA Engineer - 10+ Years - Bangalore Location
Leadic Design · Bengaluru · onsite · Posted 50d ago
Not disclosed10–12 yrsfulltimeSourced from
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About this role
Company Description LeadIC Design Pvt Ltd accelerates semiconductor innovation through full-stack VLSI engineering expertise, supporting the complete chip development lifecycle for global semiconductor companies. Founded in 2018, the company has grown into a trusted partner that delivers high-quality design services with strong execution ownership and flexible engagement models. With engineering teams across India and Canada, LeadIC provides end-to-end capabilities spanning custom layout, analog/mixed-signal design, digital design, verification, physical design, STA, DFT, and IP characterization. The organization is driven by an engineering culture built on ownership, quality-focused methodologies, and predictable delivery frameworks. LeadIC forms long-term technical partnerships with product-driven teams, enabling scalable offshore design centers and accelerating silicon success.
Role Description This is a full-time, on-site STA Engineer role based in Bengaluru South. The STA Engineer will be responsible for performing full-chip and block-level static timing analysis, including constraint development, timing closure, and signoff across multiple process nodes and performance corners. The role includes collaborating closely with physical design, RTL, and verification teams to identify timing bottlenecks, drive ECOs, and ensure robust timing quality for complex SoCs and IPs. The engineer will analyze reports for setup, hold, clock tree, and signal integrity issues, optimize timing through logical and physical changes, and maintain documentation for timing methodologies and best practices. The position also involves mentoring junior engineers, contributing to flow automation, and supporting project planning and reviews to meet schedule and quality goals.
Qualifications
Role Description This is a full-time, on-site STA Engineer role based in Bengaluru South. The STA Engineer will be responsible for performing full-chip and block-level static timing analysis, including constraint development, timing closure, and signoff across multiple process nodes and performance corners. The role includes collaborating closely with physical design, RTL, and verification teams to identify timing bottlenecks, drive ECOs, and ensure robust timing quality for complex SoCs and IPs. The engineer will analyze reports for setup, hold, clock tree, and signal integrity issues, optimize timing through logical and physical changes, and maintain documentation for timing methodologies and best practices. The position also involves mentoring junior engineers, contributing to flow automation, and supporting project planning and reviews to meet schedule and quality goals.
Qualifications
- Strong expertise in static timing analysis, including constraint development (SDC), timing closure, and signoff using industry-standard STA tools.
- Hands-on experience with physical design flows (synthesis-to-signoff), clock tree implementation, and ECO-based timing fixes.
- Solid understanding of digital design fundamentals, RTL behavior, and interaction between logical and physical design for timing optimization.
- Knowledge of signal integrity, power, and noise impacts on timing, and experience interpreting advanced timing and SI/PI reports.
- Proficiency in scripting (e.g., TCL, Python, Perl) for flow automation, report parsing, and timing analysis efficiency.
- Ability to collaborate with cross-functional teams, communicate timing issues clearly, and drive resolution in a fast-paced product environment.
- Minimum 10 years of relevant industry experience in STA or closely related VLSI domains, preferably in complex SoC or high-speed IP projects.
- Bachelor's or Master's degree in Electrical/Electronics Engineering, VLSI, or a related discipline.
- Experience with advanced technology nodes, multi-clock/multi-voltage designs, and signoff methodologies is highly beneficial
Sourced from foundit
Skills
clock tree implementationECO-based timing fixespower and noise impacts on timingreport parsingRTL behaviorSDC timing closuresignoff using industry-standard STA toolssynthesis-to-signoffStatic Timing AnalysisSignal IntegrityFlow Automationconstraint developmenttiming optimizationPhysical design flowsdigital design fundamentals