Sr Staff Engineer- RTL Design
Renesas · Hyderabad · onsite · Posted 41d ago
Not disclosed12–17 yrsfulltimeSourced from
About a minute. You'll make an account on the way through.
About this role
Responsibilities:
- Lead RTL synthesis and constraints generation/validation for MCU SoCs to meet performance, power, and area targets
- Develop and implement innovative methodologies and tools to improve design quality and engineering productivity
- Act as the key interface between frontend and backend design teams, resolving hand-off and timing-related issues
- Conduct detailed design reviews and provide feedback to peers and junior engineers
- Collaborate with cross-functional teams to resolve design collateral issues and enhance overall PPA (Power, Performance, Area)
- Support low power implementation flows and techniques
- Perform formality checks to ensure RTL vs. netlist equivalence
Sourced from foundit
Skills
ASIC development flowConstraints generationStatic Timing AnalysisSTAsoc designtiming closure
About Renesas
Renesas
Bangalore / Bengaluru, Karnataka
India
₹30.6L PA avg
Avg at Renesas
About
Renesas is a leading semiconductor manufacturer, producing various types of microchips and striving to enhance the global chipmaking industry through innovation.
Industries
ManufacturingElectronics
Employee ratings
10 reviews
3.5/ 5
Culture
3.5
Career growth
2.7
Work-life
2.7
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