BENGALURU · FULLTIME
Sr Staff Engineer - Physical Design
Tylsemi
Bengaluru · onsite · Posted 1d ago
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Undisclosed10–15 yrsfulltimeBengaluru
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Section · 01
About this role
{"company":"
About TYLsemi, Inc.
The Opportunity The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package
Thats what we solve. TYLsemi builds the chiplet infrastructure IP - the IO, power delivery, and interconnect building blocks - that makes AI/HPC systems actually work at scale.
This isnt a nice-to-have. Its the critical path.
Why Now The Market Window The semiconductor industry is going through its biggest architectural shift in 40 years:
- Moores Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.
- Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI - theyre all designing their own ASICs. The $50B custom silicon market is growing 30% annually.
- IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.
- Translation: Were entering the market at exactly the moment when every major AI/HPC player needs what were building, and their alternatives are disappearing.
There are no layers, no approval chains, no corporate theater.
- If you have an idea, we test it. If it works, we ship it.
- No endless meetings, no PowerPoint presentations to convince middle management.
- US team: Bay Area preferred, but we hire the best people regardless of location
- India team: Building a world-class design center in Bangalore
Were not a research project. We have paying customers, committed capital, and aggressive timelines.
This is a company, not a lifestyle business. Were building to win.
What We Value - Ownership mindset. Youre not here to execute someone elses roadmap. Youre here to define it.
- Bias for action. We move fast. Analysis paralysis doesnt fly here.
- Deep technical expertise. This is hard engineering. We need people whove shipped real silicon and debugged real hardware.
- Low ego, high standards. We dont care about titles or politics. We care about results.
If youre reading this, youre probably comfortable. You have a good job at a stable company with all the benefits.
Were asking you to walk away from that and bet on us.
Heres why you should:
- The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what were building.
- The team has done this before. Weve built and exited semiconductor companies at scale. This isnt our first rodeo.
- The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.
- The work is consequential. Youre not optimizing someones ad click-through rate. Youre building the silicon infrastructure that powers AI.
This is the bet. Join us and build something that matters.
Or stay comfortable. No judgment.
But if youre the kind of person who wants to take the shot, wed love to talk.
READY TO JOIN
Role Overview
We are looking for a highly skilled Senior Staff Physical Design Engineer to drive end-to-end physical implementation for advanced semiconductor designs across cutting-edge technology nodes. The ideal candidate will lead block/subsystem-level implementation activities, collaborate cross-functionally with RTL, STA, DFT, and CAD teams, and ensure high-quality tape-outs with strong focus on power, performance, and area (PPA). This role requires deep expertise in physical design methodologies, debugging complex issues, and mentoring junior engineers.
What You ll Do
- Lead full-chip or block-level physical design implementation from floorplanning to GDS signoff.
- Drive floorplanning, power planning, placement, CTS, routing, optimization, and physical verification closure.
- Analyze and optimize timing, congestion, IR drop, EM, and power for advanced technology nodes.
- Collaborate with RTL, DFT, STA, package, and CAD teams to resolve implementation and signoff challenges.
- Develop and improve physical design flows, automation scripts, and methodology enhancements.
- Support tape-out activities and ensure design signoff quality across all implementation stages.
- Mentor junior engineers and contribute to technical reviews and best practices.
What We re Looking For
- 10+ years of hands-on experience in ASIC/SOC physical design implementation.
- Bachelor s or Master s degree in Electronics, Electrical Engineering, VLSI, or related field.
- Strong expertise in industry-standard EDA tools such as Cadence Innovus, Synopsys ICC2, PrimeTime, and StarRC.
- Solid understanding of timing closure, low-power design techniques, signal integrity, IR/EM analysis, and physical verification.
- Experience working on advanced technology nodes (7nm/5nm/3nm preferred).
- Strong scripting skills in Tcl, Perl, or Python for automation and flow enhancement.
- Excellent debugging, problem-solving, communication, and stakeholder collaboration skills.
Good to Have
- Experience with hierarchical and top-level SOC integration.
- Exposure to ML/AI-based design optimization methodologies.
- Knowledge of package-aware implementation and multi-die/chiplet architectures.
Success in This Role Looks Like
- Consistent delivery of high-quality physical design milestones with minimal schedule impact.
- Successful closure of timing, power, area, and reliability metrics for complex SOC designs.
- Proactive identification and resolution of implementation bottlenecks and signoff risks.
- Positive contribution to team productivity, methodology improvements, and mentoring initiatives.
Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
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Section · 02
Skills
AutomationAI infrastructurePrimetimeMeltingCadenceHpceda toolsphysical designInnovusCritical PathPerlASICCADDFTLow-Power DesignOpenAI SDKEvent Drivendebuggingelectrical engineeringcloudPhysical VerificationGDSArtificial IntelligenceMachine Learning