Sr. Staff ASIC Design Engineer in Bangalore, KA, India

Sr. Staff ASIC Design Engineer in Bangalore, KA, India Sr. Staff ASIC Design Engineer Description

Synaptics is leading the charge in AI at the Edge, bringing AI closer to end users and transforming how we engage with intelligent connected devices, whether at home, at work, or on the move. As the go-to partner for the world s most forward-thinking product innovators, Synaptics powers the future with its cutting-edge Synaptics Astra AI-Native embedded compute, Veros wireless connectivity, and multimodal sensing solutions. We re making the digital experience smarter, faster, more intuitive, secure, and seamless. From touch, display, and biometrics to AI-driven wireless connectivity, video, vision, audio, speech, and security processing, Synaptics is the force behind the next generation of technology enhancing how we live, work, and play.

Synaptics is seeking a Sr. Staff ASIC Design Engineer to join our growing team. The ideal candidate will bring strong ASIC/SoC design expertise, lead complex design and integration activities, and collaborate across cross-functional engineering teams. This role will contribute to architecture and methodology decisions, drive technical execution from design through tape-out and silicon bring-up, and mentor other engineers. This position reports to the Sr. Director, ASIC Design.

Responsibilities & Competencies

Job Duties

• Contribute to SoC architecture, micro-architecture, design partitioning, system interfaces, clock/reset architecture, SoC integration, and RTL design of complex ASIC/SoC blocks from specification through tape-out and silicon bring-up
• Drive design tradeoffs across power, performance, area, cost, and schedule and recommend practical solutions based on system and product requirements
• Provide technical leadership for RTL design, lint, CDC/RDC, synthesis, timing constraints, and design-quality closure
• Develop and implement low-power architecture and methodologies, including UPF, power domains, isolation, retention, and power sequencing; Drive Power Analysis at chip-level
• Work closely with Verification teams to define verification requirements, debug complex failures, and drive functional and coverage closure.
• Lead technical resolution of complex pre-silicon and post-silicon issues, using structured root-cause analysis across hardware, firmware, and software boundaries.
• Develop and improve design methodologies, automation, and engineering flows to improve quality, productivity, and scalability.
• Participate in design reviews, documentation, and process improvements to ensure quality and efficiency
• Chip and IP level timing analysis and closure, timing constraint/SDC development
• Provide technical guidance and mentorship to junior engineers, contributing to team knowledge and best practices

Qualifications (Requirements)

Belief in Diversity
Synaptics is an Equal Opportunity Employer committed to workforce diversity. Qualified applicants will receive consideration without regard to race, sex, sexual orientation, gender identity, national origin, color, age, religion, protected veteran or disability status, or genetic information.