Sr/Principal Design Verification Engineer

Roles and Responsibilities

• We are seeking an experienced Design Verification Engineer to drive verification of complex next-generation AI/compute platforms. The ideal candidate will have deep expertise in SystemVerilog/UVM-based verification, strong debugging skills, and a proven track record of delivering high-quality silicon.
• The role involves developing testbenches from scratch for high speed designs such as PCIe, DDR, Ethernet, AMBA protocols, and for various internal protocol-based designs at IP, Subsystem and SoC level.
  
• Collaborate with cross-functional teams to identify requirements and develop verification plans.
  
• Create reusable functional and gate-level simulations using System Verilog.
  
• Ensure timely delivery of high-quality results by mentoring junior engineers.