Sr PD Engineer - STA & Timing Closure

Job Summary


Key Responsibilities

• Fullchip Timing analysis for multiple modes that includes Functional and DFT and interface special timing checks
• To have expertise in understanding and debugging timing issues in Fullchip level and block level
• Experience on Floor-planning, Place route, power and clock distribution, pin placement
• Role involves interaction with multiple design teams, CAD teams, Tool vendors, (on and cross sites)
• In-depth knowledge on industry leading tools like Primetime and ICC2
• Knowledge of Synthesis and DFT is added advantage
• Knowledge of constraints analysis using GCA or similar tool is added advantage
• Prior experience with 3nm or finer geometries is a plus
• Proficient use of tcl/Perl
• Must have good communication skills and self-driven individual

Qualifications

• Bachelors or Masters degree in computer engineering/Electrical Engineering with minimum 8-10 years of experience

Requirements

• You have a passion for physical design and STA in general.
• You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones.
• You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

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