Sr Engineer, Design Verification

Opportunity for a talented individual for their memory interface products.

We are looking for a candidate with a strong background in verifying complex integrated circuits.

• The candidate needs to have skills that are up to date with the latest IC verification tools and flow.
• The candidate will work closely with design, and verification engineering.
• In addition, strong collaboration and communication skills are a must.

Duties/Responsibilities:

• Develop verification testbench components for chip/module level using System Verilog.
• Use high-level concepts (Object-oriented, UVM, etc) to develop an extendable environment.
• Define and execute detailed verification plan from spec working with architects and designer engineers
• Experience in code coverage, functional coverage, assertions, cover groups, etc to achieve 100% verification completeness before tape-out.
• Debug tests, regression failures and participate in silicon debugging and analysis.

• Understanding or prior experience with Industry standard protocols like DDR4/DDR5/LPDDR5/DIMM (Dual In-line Memory Module) knowledge is preferred. Qualifications

• Bachelors or Masters in Electronics or Electrical Engineering with a minimum of 2-5 years of experience in design/verification management of highly complex projects.
• Organized and creative thinker, motivated, and independent learner who can multitask in a dynamic environment, able to create and implement new solutions where required.
• Must be good in building verification environments preferably using the verification subset of high-level languages like System Verilog (UVM).
  
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