Sr. Design Lead

Responsibilities

• 8-12 years of experience in SoC/IP Design.
• Expertise in Writing Detailed IP Specifications, Micro Architecture, IP design, Subsystem and SoC level integration.
• Expertise on RTL Development. Follow Coding Standards, expertise on Lint, CDC tools, Verification and Debugging of test cases, code and functional coverage analysis.
• In-depth knowledge of Clocking Methodology, Low Power Implementation.
• Hands on experience on writing constraints and exceptions, performing Synthesis, Timing Analysis and Design for Test Implementation.
• Experience of power partitioning and usage of CPF/UPF.
• Exposure to IP Design for ARM Microcontrollers based SoCs.
• Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB).
• Knowledge of one or more of the interface protocols, PCIe, DDR, Ethernet, I2C, UART, SPI.
• Experience in Matlab Simulations and Implementing Signal Processing IPs like Digital Filters, Math Functions or FFT engines.
• Experience in developing Security IPs for various Encryption standards.
• Experience in implementing On-chip Memory and Flash controllers.

Skills

• SoC/IP Design
• RTL Development
• Clocking Methodology
• Low Power Implementation
• Synthesis, Timing Analysis, and Design for Test
• CPF/UPF Power Intent
• ARM Microcontrollers based SoCs
• AMBA bus protocols (AXI, AHB, ATB, APB)
• Security IPs

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