Sr. Design Lead

About Us

Tessolve is one of the largest global pureplay Digital ER&D silicon design services companies offering end-to-end turnkey new product design offerings with a unique combination of pre-silicon and post-silicon DNA to provide an efficient turnkey solution from silicon bring-up, and spec to the product design lifecycle. With a global engineering team of over 3200+ employees and a presence across 12 locations worldwide, Tessolve is a comprehensive one-stop product engineering services & technology solution provider. Our full services offerings span advanced silicon, hardware design, and embedded software capabilities, setting up Global Engineering Centres (GEC) bolstered by state-of-the-art infrastructure investments in silicon and system testing labs.

Tessolve serves a diverse global clientele, including 9 of the top 10 semiconductor companies, OEMs & Tier 1 clients across multiple sectors, start-ups, and government & defense entities. Our global footprint includes offices in the United States, India, Singapore, Malaysia, Germany, United Kingdom, Canada, Netherlands, Japan, Taiwan, Thailand and the Philippines, with global delivery & testing labs strategically located in India, USA, Singapore, Germany and Malaysia.

Visit us at http://www.tessolve.com to learn more.

Key Skills And Responsibilities

• 10 to 15 years of experience in SoC/IP Design.
• Should have solid experience in very large SoC Integration in a highly complex Front-end environment
• Should have worked on at least 2 SoC integration project completing RTL freeze
• Able to analyse/define/develop/write micro-Architecture specification for a sub-system
• Interact with Architect/stakeholders and understand the Module/Sub-system requirements
• Should be able to own and drive Quality check of the sub-system (CDC, RDC, Lint, DFT Lint) and take to closure
• Able to write glue logic/gasket/bridge modules as required
• Should have solid experience in working with teams across multiple time zones
• Experience in working large SoC/Chiplet design . Designs with Multi Clock/Reset/Voltage and Power domain
• Able to review and provide timing constraints at sub-system level. Need to co-ordinate with implementation team
• Experience in High-speed protocol based sub-system like PCIE SS, Ethernet SS, LPDDR is a most preferred
• Need to be self-driven and committed.
• Need to be agile, delivering results in a dynamic SoC development
• Need to be adept in finding design solution at SoC level
  
  

Equal Opportunity Employer

At Tessolve, we are committed to fostering a workplace that embraces and celebrates diversity in all its forms. We believe that diverse teams drive innovation, creativity, and success. We are dedicated to creating an inclusive environment where all employees, regardless of their race, color, religion, gender, gender identity or expression, sexual orientation, national origin, genetics, disability, age, or veteran status, feel valued and respected. We believe in fair and equitable treatment for all employees and aim to eliminate any biases or barriers that may hinder personal or professional growth.