Sr. Design Engineer 2

Key Responsibilities

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  Develop micro-architecture specifications based on system requirements.

  
  


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  Design and implement RTL using Verilog/SystemVerilog.

  
  


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  Perform RTL coding, linting, CDC checks, and synthesis.

  
  


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  Work closely with verification teams for testbench support and debug.

  
  


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  Participate in design reviews and provide technical solutions.

  
  


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  Perform block-level and SoC-level integration.

  
  


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  Support STA, DFT, and physical design teams during implementation.

  
  


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  Analyze and debug functional and timing issues.

  
  


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  Ensure design meets power, performance, and area (PPA) targets.

  
  


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  Collaborate with cross-functional teams including firmware and validation.

  
  

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Required Skills Qualifications

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  5?8 years of hands-on experience in RTL design for ASIC/SoC.

  
  


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  Strong expertise in Verilog/SystemVerilog.

  
  


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  Experience in micro-architecture and high-speed digital design.

  
  


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  Good understanding of synthesis, STA, CDC, and low-power design concepts.

  
  


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  Experience with industry-standard EDA tools (e.g., Synopsys, Cadence, Mentor).

  
  


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  Strong debugging and problem-solving skills.

  
  


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  Knowledge of scripting languages (Perl/Python/TCL) is a plus.

  
  


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  Familiarity with AMBA protocols (AXI/AHB/APB) preferred.

  
  


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  Experience in IP integration and SoC architecture.

  
  

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Preferred Qualifications

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  Experience in high-speed interfaces (PCIe, USB, Ethernet, DDR, etc.).

  
  


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  Exposure to low-power design techniques (UPF/CPF).

  
  


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  Experience in 7nm/5nm or advanced technology nodes is an advantage.

  
  


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  Knowledge of FPGA prototyping is a plus.

  
  

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Education

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  B.E./B.Tech or M.E./M.Tech in Electronics / Electrical / VLSI / related field.

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