Sr ASIC DFT Engineer
Cisco Systems · Bengaluru · onsite · Posted 7d ago
Undisclosed7–11 yrsfulltimeSourced from
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About this role
Job Summary
Your Impact
Minimum Qualifications
Preferred Qualifications
Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
Meet the Team: The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web-scale data
Your Impact
- Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
- Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
- Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
- Your team will participate in the creation of Innovative Hardware DFT physical design aspects for new silicon device models, bare die stacked die, driving re-usable test and debug strategies.
- The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.
Minimum Qualifications
- Bachelor's or a Master's Degree in Electrical or Computer Engineering required, with at least 7-11 years of experience.
- Knowledge of the latest innovative trends in DFT, test and silicon engineering.
- Experience with JTAG protocols, Scan and BIST architectures, including memory BIST and boundary scan.
- Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime.
- Verification skills include SystemVerilog Logic Equivalency Checking and validating the Test-timing of the design.
- Experience with Gate-level simulation, debugging with VCS and other simulators.
Preferred Qualifications
- Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687
- Strong verbal skills and ability to thrive in a multifaceted environment
- Scripting skills: Tcl, Python/Perl.
Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
Sourced from naukri
Skills
CraftAtpgeda toolsChip designcomputer engineeringlaw enforcementDiagnosticsASICJTAGDFTBankingComputer NetworksEvent DrivendebuggingBISTDebugboundary scanGate level simulationArchitectureCiscoHardware DesignArtificial Intelligence
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Cisco Systems
Hardware & Networking
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1984
42 years old
Bangalore / Bengaluru, Karnataka
India
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