Sr Analog & Mixed-Signal Layout Design Engineer

We are seeking a highly skilled High-speed SERDES IO PHY Layout designer with 5 - 7 years of experience. Apart from Serdes PHY Layout, the ideal candidate should have a strong background in analog/IO design principles, hands-on experience with layout tools, Automated PnR and a passion for solving challenging technical problems.

Key Responsibilities:

• Develop and optimize Serdes PHY, analog and mixed-signal IC layouts, ensuring high performance and manufacturability.
• Collaborate with design engineers to understand design requirements and translate them into precise layouts.
• Strong experience in debugging DRC, ERC, LVS, EMIR and PERC issues independently.
• Work experience of block PnR to closely interact with physical design team ensuring area/timing/backend compatibility of custom blocks into the overall chip design.
• Identify and resolve layout-related issues, providing creative solutions to meet design specifications.
• Conduct layout reviews and provide technical feedback to improve layout practices and methodologies.
• Stay up-to-date with industry trends, tools, and technologies to continuously enhance layout processes. Qualifications

• Bachelor s or Master s degree in Electrical Engineering, Electronics, or a related field.
• 5-7 years of experience in IO/Analog mixed-signal IC layout design and block level PnR
• Proficiency in layout tools such as Cadence, Synopsys, or Mentor Graphics.
• Hands-on experience with custom layout design for various analog and IO circuits is required, including expertise in Bandgap references, LDOs, Clocking circuits, GPIOs, DDR IOs, and ESD circuits.
• Familiarity with custom digital layout (i.e. high speed logic paths).
• Knowledge of signal integrity issues (i.e. clock/data routes, differential routing, shielding).
• Strong understanding of analog/IO design principles, including parasitic effects.
• Aware of layout techniques to mitigate ESD, latch-up issues.
• Holds advanced knowledge of CMOS and FinFET technologies and their impact on design and performance issues in deep sub-micron process nodes, specifically 7nm and below.
• Experience with layout concepts that incorporate reliability considerations, including techniques for managing electromigration (EM), IR drop, and self-heating.
• Experience with layout optimization for power, performance, and area (PPA) metrics.
• Excellent problem-solving skills and attention to detail.
• Effective communication and teamwork abilities.

Preferred Skills:

• Knowledge of scripting languages (e.g., Skill,TCL, Python and SVRF) for automation tasks.