Sr Analog Layout Engineer: Non Finfet

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Position: Senior Analog Layout Engineer
Location: Bangalore
Experience: 4-8 Years
Employment Type: Full-Time

About the Role

Cyient Semiconductor is looking for a highly skilled Senior Analog Layout Engineer with strong expertise in Non-FinFET technology nodes to join our growing Analog/Mixed-Signal design team. The ideal candidate should have hands-on experience in layout implementation of complex analog and power management circuits, with a strong understanding of layout optimization techniques, matching requirements, reliability rules, and physical verification.

This role offers an opportunity to work on advanced Analog, Mixed-Signal, PMIC, and Power Management products across mature CMOS and BCD technologies.

Key Responsibilities

• Perform full-custom analog layout design from block level to top-level integration.
• Develop high-quality layouts for Analog, Mixed-Signal, and PMIC circuits.
• Work closely with Design Engineers to interpret schematics and floorplan requirements.
• Execute layout implementation adhering to performance, area, matching, and reliability constraints.
• Conduct layout reviews and ensure adherence to technology-specific design guidelines.
• Drive block-level and chip-level layout closure activities.
• Participate in tape-out and silicon bring-up support.

Layout Expertise Required

Candidate should have hands-on layout experience in:

Analog Circuit Blocks

• Bandgap References
• Current Mirrors
• Bias Circuits
• Operational Amplifiers (Op-Amps)
• Comparators
• Voltage References
• Oscillators
• ADC/DAC Related Layouts
• PLL Supporting Blocks

PMIC Blocks

• LDO Regulators
• Buck Converters
• Boost Converters
• Charge Pumps
• Power Sequencing Circuits
• Protection Circuits
• Driver Circuits

Mandatory Technical Skills

Process Technology Experience

• Strong experience in Non-FinFET nodes such as:
• 180nm
• 130nm
• 90nm
• 65nm
• 55nm
• BCD Technologies

Layout Skills

• Device Matching Techniques
• Common Centroid Layout
• Interdigitation
• Symmetry-Based Layouts
• Guard Ring Implementation
• Noise Isolation Techniques
• Latch-Up Prevention
• ESD-Aware Layout Design
• Substrate Noise Management

Physical Verification

Hands-on experience in:

• DRC Closure
• LVS Closure
• ERC Checks
• Antenna Fixes
• Reliability Verification
• EM/IR Awareness
• Density Closure

EDA Tool Experience

Strong experience using:

Cadence Tools

• Virtuoso Layout XL
• Virtuoso ADE
• Assura / Pegasus
• PVS
• QRC

Physical Verification Tools

• Calibre DRC
• Calibre LVS
• Calibre PERC

Desired Experience

• Experience in PMIC, Power Management, Industrial, Consumer, Automotive or Mixed-Signal products.
• Exposure to BCD process technologies.
• Experience handling complete block ownership.
• Work experience in multiple tape-outs.
• Understanding of analog layout parasitic impact and optimization.
• Interaction with global design and verification teams.

Good Understanding Of

• Analog Layout Methodologies
• Device Physics
• Process Variations
• Parasitic Extraction
• Reliability Concepts
• Electromigration
• IR Drop Awareness
• ESD Design Requirements
• Manufacturability Guidelines

Educational Qualification

• B.E / B.Tech / M.E / M.Tech in Electronics, Electrical, VLSI, Microelectronics, or related disciplines.

What We Are Looking For

4-8 years of Analog Layout experience
Strong expertise in Non-FinFET process nodes
Proven experience in PMIC and Analog Layout Design
Strong understanding of matching and reliability concepts
Hands-on expertise in Cadence Virtuoso and Calibre tools
Excellent communication and teamwork skills

Why Join Cyient Semiconductor?

• Opportunity to work on next-generation Analog & PMIC products.
• Exposure to advanced semiconductor development programs.
• Collaborate with industry-leading Analog and Mixed-Signal experts.
• Fast-growing semiconductor business with strong career growth opportunities.
• Work on high-impact global customer engagements.

How to Apply

Interested candidates can share their updated resume to:
[email removed]