SoC Testability Architect: Lead the Silicon Excellence Roadmap (DFT Lead)

Position Overview:

We are seeking a highly skilled and experienced DFT Lead to join our dynamic team. As a DFT Lead, you will play a pivotal role in ensuring the successful implementation of Design-for-Test (DFT) strategies and methodologies across product development lifecycle. With at least 5 years of relevant experience, you will lead and guide a team of DFT engineers to deliver high-quality, testable, and efficient designs. Your expertise in DFT techniques, tools, and industry standards will be critical in achieving our goal of producing robust and reliable semiconductor products.

Responsibilities:

• Develop and execute DFT methodologies, strategies, and guidelines to maximize test coverage, reduce test cost, and optimize production yield.
• Define and review DFT specifications, including scan, test compression, boundary scan, memory BIST, and ATPG patterns, ensuring compliance with industry standards.
• Evaluate and select appropriate DFT methodologies, considering design complexity, test coverage requirements, and time-to-market constraints.
• Work closely with the design team to influence design decisions and ensure DFT requirements are met without compromising performance, power, or area.
• Collaborate with cross-functional teams, including design, verification, and manufacturing, to define DFT requirements and drive DFT implementation throughout the product lifecycle.
• Drive continuous improvement initiatives to enhance DFT methodologies, tools, and processes, aiming for increased efficiency, quality, and reliability of DFT implementation.
• Perform DFT sign-off activities, including DFT coverage analysis, ATPG fault coverage analysis, DFT-related timing analysis, first-pass silicon bring-up and post-silicon debug.
• Stay abreast of industry trends, emerging DFT techniques, and advancements in semiconductor testing, and apply relevant knowledge to improve DFT practices within the organization.

Requirements:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum of 5 years of experience in DFT, with focus on digital and mixed signal designs in the semiconductor industry.
• Strong proficiency in DFT tools like Cadence Modus, Genus etc.
• Experience with ATPG, scan insertion, and test pattern generation for high-complexity designs.
• Hands-on experience with DFT-related EDA tools and methodologies, including scan compression, boundary scan, memory BIST, and JTAG.
• Familiarity with silicon bring-up and post-silicon debug.
• Strong knowledge of DFT techniques, methodologies, and industry standards, such as IEEE 1149.1.
• Experience in scripting languages, such as Perl or Python, for automation and data analysis is desirable.
• Strong analytical and problem-solving skills, with the ability to identify and address DFT-related issues and challenges.