SoC FV/CLP Engineer

Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group > Hardware Engineering

General Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
  
  

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Required Skills And Experience

• We are looking for a candidate with 5+ years of relevant experience in logical signoff and low-power structural verification for sophisticated SoC and IP development programs.
• Strong experience with low-power design and verification, including hands-on knowledge of UPF/CPF and SystemVerilog.
• Hands-on experience with low-power verification tools such as Cadence Conformal Low Power (CLP) or Synopsys VCLP.
• Experience with Logic Equivalence Checking (LEC) and power-aware LEC, with strong skills in analyzing and resolving verification failures.
• Ability to effectively debug CLP/VCLP and LEC issues and drive them through closure.
• Understanding of synthesis and Place & Route (P&R) flows is an advantage.
• Ability to collaborate across design, verification, and implementation teams to support successful signoff of complex SoC and IP designs.
  
  

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