SoC DFT Lead

KeyResponsibilities

SoCDFTArchitecture&Leadership

.OwnSoC-levelDFTarchitectureandstrategyforcustomandplatform-basedSoCs.

.DefineanddriveDFTimplementationplansacrossmultipleconcurrentSoCprograms.

.ActasthetechnicalauthorityandsignoffownerforallDFT-relateddecisionsanddeliverables.

Execution&TechnicalOwnership

.LeadDFTRTLintegration,scaninsertion,andtestarchitectureimplementation.

.Ownanddrive:

.Scan,Compression,andATPGstrategy

.MBIST,BISR,andredundancyimplementation

.JTAG/TAP,BoundaryScan,anddebuginfrastructure

.EnsureDFTreadinessacrossfunctional,scan,andlow-powermodes.

.CollaboratewithRTL,STA,andPDteamstoensureDFT-friendlydesignandimplementation.

.DriveATPGpatterngeneration,simulation,anddebugtoensurehightestcoverageandquality.

Cross-Functional&ManufacturingInterface

.WorkcloselywithphysicaldesignteamstoensurescanandtestlogicclosurewithminimalPPAimpact.

.Interfacewithmanufacturing,ATE,andOSATteamsontestrequirements,vectordelivery,andsiliconbring-up.

.Supportpost-silicondebug,yieldramp,andtestoptimization.

.RepresentSemifiveincustomer-facingtechnicaldiscussionsrelatedtoDFTstrategyandsignoff.

Methodology&TeamDevelopment

.DefineandstandardizeDFTmethodologies,flows,andchecklistsacrossSemifiveprograms.

.Driveautomation,scripting,andreusetoimproveDFTefficiencyandpredictability.

.MentoranddevelopDFTengineersandleads,buildingdeeptechnicalandexecutioncapability.

.ReviewandapproveDFTsignoffreportsandtapeoutreadinesscriteria.

Qualifications

.B.E./B.TechorM.E./M.TechinElectrical/Electronics/VLSIEngineering.

.12+yearsofexperienceinDFTarchitectureandimplementationforcomplexSoCs.

.ProventrackrecordofleadingDFTimplementationandsignoffonmultiplecustomSoCtapeouts.

.Strongexpertisein:

.Scan,Compression,andATPGmethodologies

.MBIST,BISR,andmemoryrepairschemes

.JTAG/TAPandBoundaryScan

.DFTRTLintegrationandpatternsimulation

.Hands-onexperiencewithindustry-standardDFTtools,suchas:

.SiemensTessent

.SynopsysDFTMAX/TestMAX

.SpyGlassDFT(orequivalent)

.Strongunderstandingof:

.Low-powerDFTchallenges(UPF/CPF)

.Scanandtest-modetimingclosure

.PhysicalimplementationconstraintsforDFT

.Experienceworkingwithmanufacturing,ATE,andpost-siliconvalidationteams.

.Excellentproblem-solving,communication,andleadershipskills.