SOC Design Implementation

For Design Implemenation:

RTL Synthesis to achieve the best Performance/Power/Area of the designs

DFT insertions that include MBIST and SCAN, setup Timing Constraints for functional and Test Modes, and Validation.

Run static Low-Power checks on gate level netlists

Verify Logic Equivalency Checks between RTL to Gates and Gates to Gates

Setup signoff Static Timing Analysis and ECO flows and achieve timing closure working with the Design/DFT/PD teams

Timing analysis with sta tools

Constraints debug and sanity checks