SMMU Senior Lead Design Verification Engineer

Ownership of System Memory Management [SMMU] IP test bench and collaterals for the next generation System-on-chip (SoC) for smartphones, tablets and other product categories. System Memory Management Unit does virtual to physical address translation, dynamic allocation and access control of DDR memory, designed as per ARM SMMU architecture spec.

Job responsibilities include

• Ownership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage)
• Develop test plan and test cases to cover design feature set, follow up with stake holders on code coverage, functional coverage closure at different levels of test bench
• Work closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure
• Debug of regression signatures and identifying bug fixes
• Developing/Deploying scripts/tools for validation (Certitude, VC Formal, Fishtail)
• Debug and root cause post silicon issues in collaboration with Design, SW and test teams
• Work with SoC level performance modeling team on latency, bandwidth analysis

Required skillset include

• Strong debugging, Analytical and problem-solving skills
• Expertise on UVM, System Verilog coding
• Knowledgeable about ARM bus protocols (AXI, AHB, APB, CHI), Virtual Memory concepts, SoC system architecture
• Experience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved
• Post-si bring-up and HW-SW debug experience would be a plus. Knowledge exposure to silicon debug tool chains would be an added advantage
• Communication and collaboration skills to work with a large world-wide design organization