SME

Role & responsibilities

• Conduct research and feasibility studies on FPGA architectures, FPGACPU/GPU codesign, and acceleration frameworks.
• Architect and prototype novel RTL modules, pipelines, and hardware algorithms.
• Develop proofofconcept (PoC) implementations to evaluate performance, latency, throughput, and resource tradeoffs.
• Explore emerging FPGA toolchains, HLS methods, and hardware optimization techniques.
• Perform profiling, benchmarking, and architectural exploration across FPGA platforms.
• Document findings, design trade-offs, and research insights for internal teams.
• Estimation of new features, Debug test failures to determine the root cause; work with other RTL and firmware engineers to resolve any issues.

Skill Requirements:

Mandatory skills:

• Handson experience in FPGA/RTL design and development
• Strong command of VHDL or Verilog/SystemVerilog for RTL development.
• Experience in developing RTL designs in one or more of the following technologies: PCIe, Ethernet, TCP/IP, Packet processing, USB, etc.
• Excellent ability to analyse and isolate RTL and test bench issues
• Proficient in using UVM testbenches and working in Linux and Windows environments
• Strong background in simulation, verification, and debugging using ILA/SignalTap.
• Solid understanding of digital design concepts, algorithms, and architectural trade-offs.
• Should be able to develop the small blocks of IP from scratch and do basic functional verification.
• Should be familiar with protocols like SPI, I2C, UART and AXI.

Desirable Skills:

• Experience with High-Level Synthesis (HLS) for algorithm acceleration.
• Exposure to SoC-based FPGA platforms (Zynq/Ultrascale+/Stratix 10/Agilex).
• Scripting for experimentation: Python, MATLAB, Tcl, Bash.
• Understanding of PCIe, Ethernet, DDR, or high-speed I/O interfaces.