Silicon Design Verification Engineer

Come join Intels Devices Development Group, responsible for creating leading Client SOCs. We envision the future of computing and design for the next generation of laptop and desktop computers. We are looking for a ready to research, design, develop, and test Intel designs as we reimagine how to build SOCs at Intel and in the semiconductor industry. Our bold purpose as a company is to create world-changing technology that enriches the lives of every person on earth and this role is instrumental in furthering our mission to shape the future of technology.

Responsibilities may include but not be limited to:

- Validation of DFx features such as Scan, SBFT,TAP, Arrays, Fuse, MBIST etc..using simulation, emulation
- Creating plans and tests for validating portions of a complex microarchitecture using written specs, RTL code and other tests as a guide
- Learning the architecture and microarchitecture by debugging failures to the root cause
- Developing and utilizing various DFT and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design
- Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models
- Engaging with IP providers and customers to define, develop and deliver necessary infrastructure and address issues found during execution
- Developing tools and methods to streamline IP development and SOC integration to deliver highest quality in shortest time possible
- Developing debugging tools and software

Minimum Qualifications:

- Must have either a BS + 5 years experience or MS + 3 years experience in Computer Science, Computer Engineering or Electrical Engineering
- Minimum 3 years experience with reading and interpreting technical specs and Register Transfer Level (RTL) code
- Minimum 3 years experience working on IP or SoC development, verification, or integration using Verilog/SystemVerilog/OVM/UVM
- Minimum 3 years experience with writing validation plans and software to implement those validation plans
- Minimum 1 year experience with UNIX or Linux

Preferred Qualifications:

- Minimum 1 year experience with computer architecture
- Minimum 1 year experience with IA-32 assembly and/or Verilog programming experience
- Minimum 2 years experience with validation or testing experience, especially in a silicon design team
- 3yrs+ experience with industry standards such as Scan, JTAG, BScan

- Experience in Coherency

Work Model for this Role