Senior Verification Engineer
Bitsilica · Hyderabad · onsite · Posted 69d ago
Undisclosed5–10 yrsfulltimeSourced from
About a minute. You'll make an account on the way through.
About this role
Roles and Responsibilities
- Design verification using SystemVerilog, UVM, and PCIe/Ethernet protocols.
- Develop testbenches for IP verification and SOC verification.
Sourced from naukri
Skills
EthernetASIC VerificationUVMSystem VerilogIp VerificationPCIESOC Verification