Senior Verification Engineer - ASIC
Avant Garde · Bengaluru · onsite · Posted 37d ago
Undisclosed8–13 yrsfulltimeSourced from
About a minute. You'll make an account on the way through.
About this role
- Senior ASIC verification role requiring 8-15 years of hands-on block, subsystem and chip-top verification.
- The incumbent will develop SystemVerilog and UVM environments and tests, work on mixed-signal devices, implement RAL and functional and code coverage, run gate-level simulations across PVT corners and support DFT and ATPG simulations.
- Scripting in Perl, Python or Shell, collaboration with analog and architecture teams, FPGA-based validation, lab bring-up and customer-debug support are also required.
- This is a full-time work-from-office role in Bengaluru.
Sourced from naukri
Skills
AtpgMixed Signalcode coverageASIC VerificationUVMSystem VerilogFPGADFTFunctional CoverageGate level simulationRALmixed signal verification
About Avant Garde
Avant Garde
Management Consulting
59
employees
2017
9 years old
Mumbai, Maharashtra
India
₹6.5L PA avg
Avg at Avant Garde
About
Avant Garde operates within India's emerging market by connecting skilled professionals focused on innovation and transformative solutions.
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Management Consulting
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